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| CXA3003R Baseband analog processing IC for dual-mode CDMA/FM cellular phone For the availability of this product, please contact the sales office. Description The CXA3003R is a baseband analog processing IC for dual-mode CDMA/FM cellular phone. The CXA3003R interfaces between the inter-frequency section and the digital processing circuitry of the telephone. The receive circuit functions primarily convert analog IF signals to the analog baseband frequency range and to convert the analog baseband signals into digital signals. Transmit circuits convert digital data into analog baseband signals which are then up-convert to the IF frequency range. Features * Receive signal path includes: * IF to baseband down conversion * Built-in trim-free low-pass filter for CDMA and FM * Built-in A/D convertor convert the RX base band signal to the digital signal * Analog output Receive Signal Strength Indicator (RSSI) for CDMA * Local Oscillator for I-Q mixer * Transmit signal path includes: * Built-in D/A convertor convert the digital I-Q data to the analog baseband signal * Built-in trim-free low-pass filter for CDMA and FM * Baseband to IF up-conversion * Local Oscillator for I-Q mixer * Built-in PLL for TX IF * Built-in House keeping A/D convertor * Low power consumption in all modes * Single 3.3 V power supply Applications * dual-mode CDMA/FM cellular telephone 80 pin LQFP (Plastic) Absolute Maximum Ratings (Ta=25 C) * Supply voltage VCC -0.3 to 5.5 * Operating temperature Ta -55 to +125 * Storage temperature Tstg -65 to +150 Recommended Operating Conditions * Supply voltage VCC 3.30.165 * Operating temperature Ta -40 to +85 V C C V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. --1-- E96434-TE CXA3003R Block Diagram GND BUFF VDD BUF RXQD3 RXQD2 RXQD1 CHIPX8 RXQD0 TXCLKB RXID3 RXID2 RXID1 TXCLK RXID0 TXD5 TXD4 TXD7 TXD3 60 RXFMSTRB 61 FMCLK 62 59 58 57 56 55 54 53 52 51 50 49 48 47 46 TXD6 45 44 43 42 TXD2 41 40 39 TXD0 GND ESD VDD DAC GND DAC NC NC DNC DNC CAP2 CAP1 NC TCXO4 NC NC TCXO NC LOCK DET VDD TXF GND TXF VDD SYNTH CDMA Q ADC CDMA I ADC Q DAC RXIFMDT 64 DNC 65 DNC 66 I DAC RXQFMDT 63 TXD1 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 FMQ ADC FMI ADC CDMA Q RX LPF CDMA Q TX LPF GND ADC 67 VDD ADC 68 QOFFSET 69 IOFFSET 70 HKADVCC 71 NC 72 FM Q RX LPF FM I RX LPF CDMA I RX LPF CDMA I TX LPF FM TX LPF CHIP X8 ADCDT 74 VCO ADCIN 76 VCO IDLEB 78 FMB 79 RXVCOOUT 80 RSSI SLEEPB 77 MODE CNTL 1 GND 2 RXVCO T1 3 RXVCO T2 4 GND RXIF 5 VDD RXIF 6 RXIFB 7 RXIF 8 RSSI 9 GND RX 10 11 12 13 14 15 16 17 PD 18 ADCENBL 75 1/2 ADCCLK 73 HK ADC PLL 1/2 1/4 19 --2-- GND SYNTH TXIF GND TXIF VDD TXIF FM MOD TVCO T2 TVCO T1 PD ISET VDD RX PD OUT TXIFB CXA3003R Pin Description Pin No. 1 Symbol Typical Voltage (V) DC AC 0V 2 3 VDD RXIF Equivalent circuit Description GND Negative power supply pin. 2 RXVCO TI 1k 1k Receive VCO tuning pins. Connected to an external LC tank circuit for setting the receive VCO frequency. 3 RXVCO T2 GND RXIF 4 5 GND RXIF VDD RXIF 0V 3.3 V Negative power supply pin for RXIF block. Positive power supply pin for RXIF block. VDD RXIF 6 RXIFB 2V 250 250 2k 2k 6 7 Analog differential receive IF input pins. 2k 2k 7 RXIF 2V GND RXIF VDD RXIF 150 8 RSSI 8 Analog RSSI output pin. GND RXIF 9 10 GND RX VDD RX 0V 3.3 V --3-- Negative power supply pin for RX block. Positive power supply pin for RX block. CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD TXIF 11 TXIFB 2.1 V 400 400 11 12 200 200 Analog differential transmit IF output pins. 12 TXIF 2.1 V GND TXIF 13 14 GND TXIF VDD TXIF 0V 3.3 V VDD TXF Negative power supply pin for TXIF block. Positive power supply pin for TXIF block. 150 15 FM MOD 1.5 V 15 Analog baseband signal output pin for FM. GND TXF 16 17 VDD TXIF 16 TVCO T1 1k 1k Transmit VCO tuning pins. Connected to an external LC tank circuit for setting the transmit VCO frequency. 17 TVCO T2 GND TXIF --4-- CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD TXF 150 18 PD ISET 0.64 V 18 Current of PD OUT setting pin. GND TXF VDD TXF 6.25k 150 19 PD OUT 19 Transmit synthesizer charge pump output pin. 6.25k GND TXF 20 21 22 23 GND SYNTH 0V VDD SYNTH 3.3 V GND TXF VDD TXF 0V 3.3 V VDD SYNTH Negative power supply PLL block. Positive power supply PLL block. Negative power supply TX block. Positive power supply TX block. pin for pin for pin for pin for 150 24 LOCK DET 24 Transmit IF synthesizer lock detect output pin. GND SYNTH --5-- CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD SYNTH 150 26 26 TCXO 2.2 V 20k 20k Input pins for External clock 19.68 MHz (TCXO). GND SYNTH 39 25 27 28 30 35 36 GND ESD 0V Negative power supply pin. NC Don't connect pins. VDD DAC 150 29 TCXO4 29 Output pin for TCXO/4 frequency. GND ESD VDD RX 31 32 CAP1 CAP2 31 32 The pins for External Capacitor. GND RX 33 34 37 DNC GND DAC 0V --6-- Don't connect any line to this pin. Negative power supply pin for TXDA block. CXA3003R Pin No. 38 Symbol Typical Voltage (V) DC AC 3.3 V Equivalent circuit Description Positive power supply pin for TXDA block. VDD DAC VDD DAC 40 to 47 TXD0 to TXD7 40 41 42 43 45 60k 46 47 48 49 Transmit Data input pins for Transmit 8 bit D/A converter. TXD7 is the MSB. 48 49 TXCLK, TXCLKB 44 Differential transmit Clock input pins for Transmit 8 bit D/A converter. GND DAC 50 51 GND BUF VDD BUF 0V 3.3 V Negative power supply pin for A/D output block. Positive power supply pin for A/D output block. VDD BUF 52 CHIP x 8 Output pin for CHIPx8 divider with a ratio of 512/1025xTCXO. 57 52 53 to 56 57 to 60 RXID0 to RXID3 RXQD0 to RXQD3 53 58 54 55 56 59 60 Output pins for Receive CDMA 4 bit A/D converter of I signal. RXID3 is the MSB. Output pins for Receive CDMA 4 bit A/D converter of Q signal. RXQD3 is the MSB. GND BUF VDD ADC 61 RXFMSTRB 61 62 100k Strobe input pin for Receive FM 8 bit A/D converter. 62 FMCLK GND ADC Clock input pin for Receive FM 8 bit A/D converter. --7-- CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD BUF 63 RXQFMDT Q serial data output pin for Receive FM 8bit A/D converter. 63 64 64 RXIFMDT GND BUF I serial data output pin for Receive FM 8bit A/D converter. 65 66 67 68 DNC GND ADC VDD ADC 0V 3.3 V Don't connect any line to this pins. Negative power supply pin for A/D converter block. Positive power supply pin for A/D converter block. VDD RX 69 QOFFSET 1.5 V 30k 30k Receive Q channel offset adjust input pin. 142k 142k 22k 150 70 69 70 IOFFSET 1.5 V 100k 150 Receive I channel offset adjust input pin. GND RX 71 72 HKADVCC NC 3.3 V Positive power supply pin for HKA/D converter block. Don't connect pin. --8-- CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD BUF 73 ADCCLK Clock output pin for House Keeping 8 bit A/D converter. 73 74 74 ADCDT GND BUF Serial data output pin for House Keeping 8 bit A/D converter. VDD BUF 60k 75 75 ADCENBL Enable input pin for House Keeping 8 bit A/D converter. GND BUF HKADVCC 76 ADCIN 1.5 V 76 48.5k A/D analog input pin for House Keeping 8 bit A/D converter. GND ADC --9-- CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD ADC 77 77 78 79 SLEEPB, IDLEB, FMB 150 78 0V 79 Test mode switch pins. These pins control this IC function mode (1). GND ADC VDD RXIF 80 RXVCOOUT 80 Receive VCO output pin connected the external PLL IC. GND RXIF 1 Function Mode Function Mode CDMA RXTX CDMA Idle CDMA Sleep FM RXTX FM Idle FM Idle (Transition) FM RXTX (Transition) CDMA Sleep (Transition) FMB high high high low low low low high IDLEB high low low high low low high high SLEEPB high high low high high low low low Mode functions explain: 1. CDMA RXTX : This mode requires everything except the FMspecific circuits to be operating. 2. CDMA Idle : This mode powers down all transmit circuits and FM receive. 3. CDMA Sleep : This mode powers down everything except the TCXO divider and TCXO/4 output driver. 4. FM RXTX : This mode powers down all CDMA-specific circuits except the CHIPx8 synthesizer. 5. FM Idle : This mode powers down all transmit and CDMA Receive circuits. --10-- CXA3003R Electrical Characteristics DC Characteristics (VDD=3.3 V5 %, Ta=40 C to 85 C) Typ. 40 25 2 30 16 Max. 57 35 3 45 21 0.3xVDD 0.4 100 15 15 Unit Item Symbol Condition Min. Power supply current - CDMA RXTX IDD1 Power supply current - CDMA Idle IDD2 Power supply current - CDMA sleep IDD3 Power supply current - FM RXTX IDD4 Power supply current - FM Idle IDD5 1 Logic High level input voltage VIH 0.7xVDD 1 Logic Low level input voltage VIL 1 Logic High level output voltage VOH 2.7 1 Logic Low level output voltage VOL 1 Logic input Leakage current IL -100 1 Input capacitance Digital input Cin-d 1 Load capacitance Digital output Cl-d 1 Load resistance Digital output Rl-d 100 k 1 : Logic Input pins = 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 61, 62, 75, 77, 78, 79 Logic Output pins =52, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64, 73, 74 AC Characteristics TXCLK/TXCLKB vs. TXIQDATA for CDMA mode Item Data Setup to TXCLK/TXCLKB Transition Data Hold after TXCLK/TXCLKB Transition Symbol tsua tha Condition mA V A pF VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. 50 ns 50 Max. Unit TXCLK (input) TXCLKB (input) tsua tha TXQDATA (input) TXCLK=4.9152MHz TXQ Data TXI Data Fig. 1 TXCLK/TXCLKB vs. TXIQDATA Timing Diagram for CDMA mode CHIPx8 vs. RXIQDATA Item Data Output stable prior to CHIPx8 fall Data Hold after CHIPx8 fall CHIPx8 raise time CHIPx8 fall time VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. Max. Unit 20 15 ns 3 7.2 10 % to 90 %, Cload=15 pF 3 9.9 Condition --11-- Symbol tsub thb trb tfb CXA3003R tsub Chip x 8 (output) thd RXIData RXQData (output) Fig. 2 CHIPx8 vs. RXIQDATA timing diagram TXCLK vs. RXDATA for FM mode Item Data setup to TXCLK transition Data Hold after TXCLK transition Symbol tsuc thc Condition VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. Max. Unit 2.08 s 2.08 TXCLK (input) TXCLKB (input) tsuc thc TX DATA (input) TXCLK=120kHz XXXX TX Data XXXX TX Data XXXX Fig. 3 TXCLK vs. RXDATA mode timing diagram for FM FMCLK, RXFMSTROBE vs. RXFMDATA (I, Q) VDD=3.3 V5 %, Ta=-40 C to 85 C Item Symbol Condition Min. Typ. Max. Unit Strobe input valid to CLK Falling Edge tsud-s 0.69 Strobe input valid after CLK Falling Edge thd-s 2.08 Data out valid to CLK Rising Edge tsud-d 1.38 s Data out valid after CLK Rising Edge thd-d 1.38 CLK High Time tclk-hi 1.38 CLK Low Time tclk-lo 1.38 RXFMDATA (I, Q) raise time trd 3 7.2 10 % to 90 %, Cload=15 pF ns RXFMDATA (I, Q) fall time tfd 3 9.9 --12-- CXA3003R tclk-hi thd-d thd-s FMCLK (input) tclk-lo FMRXSTROBE (input) tsud-s tsud-d FXRXDATA (I, Q) (output) LSB+1 FMCLK=360kHz FMRXSTROBE=40kHz LSB XXX MSB MSB-1 LSB Fig. 4 FMCLK, FMRXSTROBE vs. RXFMDATA (I, Q) timing diagram Note : FM RXSTROBE pulse width must be one FMCLK period. ADCENABLE & ADC CLK vs. ADC DATA (VDD=3.3 V5 %, Ta=-40 C to 85 C) Item Symbol Condition Min. Typ. Max. Unit Enable True to first Clock output ten-clk 6 s Enable Pulse to end of conversion tdEn-EOC 16.8 Data out valid to CLK rising edge tsue-d 600 ns Data out valid after CLK rising edge the-d 600 Enable True Pulse width ten-pw 10 s Output raise time tre 7.2 10 % to 90 %, Cl=15 pF ns Output fall time tfe 9.9 ADCENABLE ten-pw tsue-d ADCCLK ten-clk the-d ADCDATA MSB LSB tdEn-EOC ADCCLK=820kHz (TCXO/24) Fig. 5 ADCENABLE & ADC CLK vs. ADC DATA timing diagram --13-- CXA3003R VHF Local Oscillator Item VCO output Frequency Range Lock mode charge pump Output Current Acquisition Mode charge pump Output Current Maximum Iout Adjustment Range Acquisition Mode Disable Frequency Range Phase Detector Output Compliance Voltage Phase Detector Output Impedance Reference Input Frequency Phase Detector Frequency Reference Spurs Lock Detect Pull Down Voltage Lock Detect Off Leakage Current Phase Detect Unlock Deviation Threshold during FM Rate Tank Circuit Input Impedance External VCO Input Levels Symbol fvcot Icplt Icpat Icpmaxrt Condition VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. Max. 260.76 15.5 160 18.6 A Rset=40 k Using Rset to vary nominal output current Acquisition mode initiated only by transition to any TX active mode 128 -40 192 +40 % Unit MHz Rset=40 k 12.4 fadt -1 k +1 k Hz Vopdt Zopdt freft fpdt rst VLldt ILedt PDfhdt PDfhrt Zit Vext 0.4 1M Ref.frequency/16 Rload10 k to VDD VO=VDD Measured at TXIF Nominal Impedance into each pin 300 1.5 k 200 2k 600 2M 19.68 1.23 -80 VDD-0.4 V MHz MHz dBc V A kHz Hz mVp-p 0.4 10 12 2.5 k 800 Receive VCO Item VCO output Frequency Range VCO Output Voltage Swing at 170 MHz Tank Circuit Input Impedance Symbol fvcor Vovr Zir Condition VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. Max. 170.76 147 2k 2.5 k Unit MHz mVrms Into 500 //5 pF load, AC coupled load Nominal impedance into each pin 100 1.5 k --14-- CXA3003R CDMA Receive Item Input Signal Level CDMA Sinusoid Single Tone jammer Desense Input Center Frequency Input Resistance Input Capacitance Input Referred Noise Spurious Content Jammer Related Spurious Content Offset Adjust Gain Offset Adjust Input Impedance A/D Converter Linearity Signal Path Gain Accuracy, Part to Part Signal Path Gain Accuracy, Total CDMA RX Residual Sideband Product Filter Attenuation Gain Flatness vs. Frequency Symbol Vincdcr Vinscr Jdcr ficcr Ricr Cicr IRNcr SCcr Jrscr Gadjocr Ziocr Ladcr Gspcr Gstcr RSpcr FA1cr FA2cr Gfcr 900 kHz 1.2 MHz 1 kHz to 630 kHz Condition VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. Max. Unit 0.9 mVrms 5.38 mVp-p 0.13 0.5 dB 85.38 220.38 MHz 500 650 1.5 pF 70 -40 -32 -60 -50 135 -25 -18.4 -40 Vrms dBc dBc 900 kHz offset Differential From each pin to GND Sum of I&Q,measured from 1 kHz to 630 kHz Total of all harmonic and non-harmonic power Peak in-band spurious products 375 Full scale At nominal temp and VDD Over part to part, VDD, temp %Full scale/V 100 k 170 k 220 k LSB -1.6 -2.1 1.6 dB 2.1 21 46 48 50 62 2.0 dBc dB dBp-p --15-- CXA3003R CDMA Transmit Item Symbol VDD=3.3 V5 %, Ta=-40 C to 85 C Condition I&Q in Quadrature Full Scale Signals.At nominal VDD and temp Differential From each pin to GND Min. 267 495 Typ. 300 500 40 35 30 dBc Sfdr3ct Csct Sfdr5ct Snr1ct Snr2ct focct Gerrct Perrct Afct I&Q in Quadrature, Full Scale Signals Even Harmonics Odd Harmonics IF0.1 M to IF<1.98 M IF1.98 M to IF<44 M In band, Measured at TX IF In band, Measured at TX IF Including SIN(X)/X 57 18 20 8 104 117 32 50 Max. 337 505 5 50 Unit mVp-p pF Output Amplitude of Lower Sideband Voct Load Resistance Load Capacitance Output impedance Spurious Free Dynamic Range, In Band Spurious Free Dynamic Range,Bandedge Spurious Free Dynamic Range, Out of Band Carrier Suppression Spurious Free Dynamic Range :IF Harmonics Signal to Noise Ratio,Noise Band1 Signal to Noise Ratio,Noise Band2 Output Center Frequency I, Q Gain Mismatch I, Q Phase Imbalance Amplitude Flatness vs. Frequency, 1 kHz to 630 kHz Rlct Clct Zoct Sfdr1ct Sfdr2ct 11 124 124 130.38 0.2 2 0.6 dBc/Hz MHz dB degree dBp-p 0.8 8 1.0 CDMA CHIPX8 Item Input Frequency Output Frequency Stabilization Time Symbol fic8 foc8 tsc8 Condition TCXO TCXO x 512/1025 upon mode charge VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. Max. 19.68 9.8304 10 Unit MHz s --16-- CXA3003R FM Receive Item Input Signal Level Single Tone jammer Desense Input Center Frequency Input Resistance Input Capacitance Input Referred Noise Spurious Content Jammer Related Spurious Content Offset Adjust Gain Signal Path Gain Accuracy, Part to Part Signal Path Gain Accuracy,Total FM RX Residual Sideband Products Gain Flatness vs. Frequency Filter Attenuation Symbol Vinfr Jdfr ficfr Rifr IRNfr SCfr Jrfr Gadjfr Gspfr Gspfr Gstfr RSpfr Gffr FA1fr FA2fr Condition 60 kHz offset Differential From each pin to GND Sum of I&Q,measured from 100 Hz to 15 kHz At nominal temp Peak in-band spurious product VDD=3.3 V5 %, Ta=-40 C to 85 C Min. Typ. 1.53 0.07 85.38 500 1.5 Max. Unit mVrms 0.35 dB MHz 650 pF 38 -56 -32 -60 At nominal VDD and temp Over part to part ,VDD, temp From 100 Hz to 12.2 kHz >45 kHz >60 kHz -1.3 -2.1 27 48 60 0.4 68 69 1 -50 -42 -18.4 -40 1.3 dB 2.1 dBc dBp-p dB %Full scale/V Vrms dBc 375 --17-- CXA3003R FM Transmit Item IF Output Amplitude IF Load Resistance IF Load Capacitance IF Output impedance IF Signal to Noise Ratio, Noise Band1 IF Output Amplitude Variation IF Output Amplitude Drift Maximum Spurious Content : TX IF Harmonics FM Mod Output Voltage FM Mod load Resistance FM Mod Amplitude Variation FM Mod Spurious Free Dynamic Range, to 120 kHz FM Mod Signal to Noise Ratio, 1 kHz to 15 kHz Amplitude Flatness vs. Frequency, DC to 10 kHz Symbol Voifft Rlifft Clifft Zoft Snr1ft Voifvft Voifdft Sceft Scoft Vmodft Rmodft Vmodvft Sfdrft Over part to part , VDD and temp Two tone inputs Condition VDD=3.3 V5 %, Ta=-40 C to 85 C Min. 124 495 Typ. 140 500 40 IF0.1 M to IF<44 M Over part to part , VDD and temp Over full VDD and temp ranges Even Harmonics Odd Harmonics Full scale, nominal VDD and temp 110 -1.6 -1 117 1.6 dB 1 -20 -8 610 dBc mVp-p 1.2 dB 40 87 44 100 0.6 dBc/Hz dBp-p Max. 161 505 5 50 Unit mVp-p pF dBc/Hz At nominal VDD and temp Differential From each pin to GND -10.5 490 10 k -1.2 575 Shrfmodft Single tone, full scale Afft Including SIN (X) / X TCXO Item Input Frequency Input Amplitude Input Impedance TCXO Divide Ratio TCXO / 4 Output Amplitude Symbol fitc Vitc Zitc Rtdtc Vo-tc Condition From TCXO AC Coupled VDD=3.3 V5 %, Ta=-40 C to 85 C Min. 0.5 5k 4 Into 10 k // 10 pF AC coupled Load 1 Vp-p Typ. 19.68 Max. 2 Unit MHz Vp-p --18-- CXA3003R RSSI Item Dynamic Range Gain Gain Drift Output Signal Level Output Load Resistance Full Scale Rise/Fall Time Nominal Setpoint Symbol DRrs Grs Gdrs Vors Rlrs trrs/tfrs Nsprs Condition VDD=3.3 V5 %, Ta=-40 C to 85 C Min. 25 32 -1.6 0.5 50 k 0.8 Typ. Max. 75 1.6 2.5 30 2.0 Unit dB mV/dB dB V s V At nominal temp and VDD Over VDD and Temp At nominal temp and VDD HK ADC Item Resolution Input Voltage Range Midscale Output Code Error DLE ILE Conversion Time Input Impedance Symbol Reshk Vihk Emidhk Dlehk Ilehk tchk Zihk Condition VDD=3.3 V5 %, Ta=-40 C to 85 C Min. 8 1.79 -16 -1 -1.25 20 k Typ. 2 Max. 2.24 16 1 1.25 40 Unit Bits V code LSB s Internal Voltage referenced V (ADCIN)=1.5 V At nominal temp and VDD --19-- CXA3003R Electrical Characteristics Measurement Circuit D/A converter D/A converter D/A converter Pattern Generator D/A converter D/A converter Pattern Generator 1n 100k 100k 100k 100k 100k 100k 100k 100k 100k 0.01 RXQD0 RXID1 RXQD3 GND BUFF RXQD2 RXID3 RXID0 TXD7 TXD4 TXCLKB CHIPX8 RXQD1 RXID2 TXD6 TXD3 61 100k 100k VDD BUF TXCLK TXD5 TXD2 TXD1 TXD0 SerialParallel Converter SerialParallel Converter SerialParallel Converter 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RXFMSTRB FMCLK RXQFMDT RXIFMDT DNC DNC GND ADC VDD ADC QOFFSET IOFFSET 40 39 0.01 62 63 64 65 66 GND ESD VDD DAC GND DAC NC NC DNC DNC CAP2 CAP1 38 37 36 35 34 0.01 0.01 67 68 69 70 1n 33 32 CXA3003R HKADVCC NC ADCCLK ADCDT ADCENBL ADCIN SLEEPB IDLEB FMB RXVCOOUT NC TCXO4 NC NC TCXO NC LOCK DET VDD TXF GND TXF VDD SYNTH 0.01 71 72 73 74 75 76 77 78 79 80 30 29 28 27 26 25 24 1n 100k 100k 0.01 31 1n 0.01 23 22 21 10k RXVCO T1 RXVCO T2 GND RXIF 0.01 VDD RXIF GND TXIF VDD TXIF GND RX PD ISET VDD RX PD OUT 1 2 50 3 4 0.01 1n 5 6 7 8 9 10 0.01 1n 11 12 13 14 15 16 50 17 18 19 39k 0.01 1n 1:1 1:3 1:1 A 10k V Spectrum Analyzer --20-- 1:1 51k GND SYNTH 100p TVCO T2 RXIFB TXIF FM MOD 500 RSSI TXIFB TVCO T1 GND RXIF 20 1n 1n Oscilloscope 1n CXA3003R Application Circuit To Digital Processing section From Digital Processing section To Digital Processing section From Digital Processing section To Digital Processing section 1n 100k 100k 100k 100k 100k 100k 100k 100k 100k 0.01 60 RXQD3 59 RXQD2 58 RXQD1 57 RXQD0 56 RXID3 55 RXID2 54 RXID1 53 RXID0 52 CHIPX8 51 VDD BUF 50 GND BUFF 49 TXCLKB 48 TXCLK 47 TXD7 46 TXD6 45 TXD5 44 TXD4 43 TXD3 42 TXD2 41 TXD1 TXD0 61 100k 100k RXFMSTRB FMCLK RXQFMDT RXIFMDT DNC DNC GND ADC VDD ADC QOFFSET IOFFSET 40 39 0.01 62 63 64 65 66 GND ESD VDD DAC GND DAC NC NC DNC DNC CAP2 CAP1 38 37 36 35 34 0.01 0.01 67 68 69 70 1n 33 32 1n CXA3003R HKADVCC NC ADCCLK ADCDT ADCENBL ADCIN SLEEPB IDLEB FMB RXVCOOUT NC TCXO4 NC NC TCXO NC LOCK DET VDD TXF GND TXF VDD SYNTH 0.01 1n 100k 100k 72 73 74 75 76 77 78 79 29 28 1n 27 26 25 24 0.01 23 22 21 100p RXVCO T1 RXVCO T2 0.01 80 GND RXIF VDD RXIF GND TXIF VDD TXIF TVCO T2 FM MOD TVCO T1 GND RX PD ISET VDD RX PD OUT 1 2 3 4 5 6 7 8 51k 9 10 0.01 1n 11 12 13 14 15 22k 16 17 18 39k 19 0.01 1n 100n 56p 1T367 2p 56p 1T367 From Receive RF Circuits 10k PLL 10k 0.01 1n 47n 220 680p To Transmit RF Circuits 1T367 10k 0.86 1.8k 1T367 10k 1n 22p 8p 22p Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. --21-- GND SYNTH RXIFB RSSI TXIFB GND RXIF TXIF 20 1n 1n 1n 71 30 0.01 31 Amp CXA3003R Description of Operation 1. Overall operations This IC bridges the gap between the analog RF processing and digital processing sections of the cellular telephone. Figure 6 illustrates the general circuit blocks in the portable cellular telephone employing this IC. The analog inputs and outputs of this IC interface directly with the IF (intermediate frequency) transmit/receive circuitry of the telephone. The digital inputs and outputs of this IC interface directly with the digital processing section. The RF receive circuitry acquires the low-level forward link signal from the base station (cell site) and down-converts to the IF frequency band. The RF transmit circuitry takes CDMA or FM modulated analog IF from this IC, up-converts to the channel frequency, and outputs controlled reverse link power levels to the antenna. The digital processing section includes CDMA modulation/demodulation , digital FM modulation/demodulation, voice processing, and a keypad interface. The CODEC (coder-decoder) block interfaces the telephone microphone and earpiece to the digital processing section. This IC receive signal path down-converts the acquired IF signal to baseband where it is then converted to digital data. The digital baseband signals are sent to the digital processing section for demodulation. When transmitting, the digital processing section sends modulated digital baseband signals to this IC for up-conversion to the analog IF frequency. This IC consists of a receive signal path, a transmit signal path, clock synthesis and buffering circuits, mode control logic, and a House Keeping analog-to-digital converter (ADC). Antenna RF Transmit/ Receive Processing CXA3003R Baseband Analog Processor The digital processing Mobile Station Modem CODEC Fig. 6 Dual-mode CDMA/FM cellular Telephone Block 2. CDMA Receive Signal Path This IC receive signal path (see Fig.7) is designed to accept a differential IF signal with CDMA spread spectrum modulation extending 630 kHz from the IF center frequency of 85.38 MHz. The incoming IF is reduced to I and Q baseband components by mixing with 85.38 MHz local oscillator (LO) signals in quadrature followed by low-pass filtering. The 85.38 MHz I and Q LO signals are generated on this IC. The receive VCO is set 170.76 MHz by an external varactor-tuned resonant tank circuit (inductor L and capacitor C connected in parallel). An external phase-lock loop and loop filter network provide the feedback to the varactors which tune the VCO to 170.76 MHz. A master-slave divide-by-two circuit generates I and Q signals in precise quadrature for the mixers. --22-- CXA3003R RXFMSTROBE FMCLK QOFFSET IOFFSET RXVCO T1 RXVCO T2 RXIFB RXIF FM Q RX LPF FM I RX LPF CDMA Q RX LPF CDMA I RX LPF CHIP X8 FM Q ADC FM I ADC CDMA Q ADC CDMA I ADC RXQFMDATA VCO 1/2 RXIFMDATA RXQD3 RXQD2 RXQD1 RXQD0 RXID3 RXID2 RXID1 RXID0 RSSI CHIPX8 TCXO4 TCXO RSSI 1/4 Fig. 7 Receive Section Block Diagram of CXA3003R 3. CDMA Low-Pass Filtering After mixing, the receive signal path splits into CDMA and FM sections. For CDMA, the baseband signal extends from 1 kHz to 630 kHz. Frequency components above 750 kHz are out-of-band for CDMA operation. The mixers and the subsequent CDMA low-pass filters combine to form the down-converter which outputs the CDMA baseband signals. The passband, transition band, and rejection band characteristics of these low-pass filters, in conjunction with external IF bandpass filtering, contribute to the ability of the receiver to select the desired baseband signals from the jamming effects of unwanted signals. The need to control the offset at the inputs of the ADCs is critical to the receive signal path and the digital processing section. The offset control inputs : IOFFSET and QOFFSET, are provided for this purpose. 4. CDMA Analog-to-Digital Conversion Analog I and Q baseband components are converted to digital signals by the two identical 4-bit flash (parallel) ADCs. The CDMA ADCs output a new digital value on each falling edge of the ADC clock signal, CHIPx8. The CHIPx8 ADC clock frequency of 9.8304 MHz is synthesized from the system crystal oscillator frequency of 19.68 MHz. The system crystal oscillator frequency is applied to the TCXO input of this IC. 5. FM Receive Signal Path The receive signal path for FM operation is similar to that for CDMA operation. Differences lie in the characteristics of the I and Q low-pass filters and the ADCs. The IF frequency is the same as in CDMA (85.38 MHz), but the modulation can only extend 15 kHz from the IF center frequency, forming a 30 kHz wide channel. The low-pass filters for FM operation have a much lower bandwidth than those used in CDMA. The offset of the FM low-pass filters is controlled just like the CDMA low-pass filters by the IOFFSET and QOFFSET input pins. The lower bandwidth of the FM baseband signal gives rise to the use of very low power 8-bit successiveapproximation ADCs. The FM I and Q analog baseband signals are sampled and held during the analog to digital (A/D) conversion process. The A/D conversion is initiated with a external strobe signal. A serial data stream is output beginning with the most significant bit (MSB) of the result. --23-- CXA3003R 6. CDMA Transmit Signal Path This IC transmit signal path (see Fig.8) accepts digital I and Q baseband data from the digital processing section and outputs modulated IF centered at 130.38 MHz to the RF transmitter. CDMA Q TX LPF CDMA I TX LPF FM TX LPF TXCLKB TXCLK TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 TCXO PD ISET Q DAC TXIFB I DAC TXIF FM MOD 1/2 VCO TVCO T2 TVCO T1 PLL PD PD OUT LOCK DET Fig. 8 Transmit Section Block Diagram of CXA3003R 7. CDMA Digital to Analog Conversion and Filters Eight bits of I and Q transmit data are input to the CDMA digital to analog converters (DACs) by multiplexing over an 8-bit input port on the this IC. The transmit data rate is twice as fast as the differential transmit clock, TXCLK and TXCLKB. Incoming data that is valid during the rising edge of the transmit clock is registered into the I DAC. Incoming data that is valid during the falling edge of the transmit clock is registered into the Q DAC. I and Q transmit data values have been compensated in the digital processing section to account for their 1/2 clock cycle time difference. The frequency spectrum at the output of the CDMA DACs contains unwanted frequency components due to DAC output transition edges and transients. The transmit clock frequency and harmonics are found in the spectrum and are also undesirable. Each CDMA DAC is followed by an anti-aliasing low-pass filter with a bandwidth of 630 kHz that reduces unwanted frequency components. Unlike the low-pass filters in the receive signal path, these do not require offset controls. 8. Up-Converting to IF This IC transmit path outputs a differential IF signal with CDMA spread spectrum modulation extending 630 kHz from the transmit IF center frequency of 130.38 MHz. The analog I and Q baseband components from the CDMA low-pass filters are mixed in quadrature with I and Q LO signals at 130.38 MHz. After mixing, the I and Q IF components are summed and output differentially. The 130.38 MHz I and Q LO signals are generated on this IC. The transmit VCO is set to 260.76 MHz by an external varactor-tuned resonant tank circuit. An internal phase-lock loop and external loop filter network provides the feedback to the varactors which tune the VCO precisely to 260.76 MHz. A masterslave divide-by-two circuit generates I and Q signals in precise quadrature for the mixers. --24-- CXA3003R 9. FM Transmit Signal Path An analog FM modulation signal is constructed from 8-bit digital data supplied by the digital processing section. Only the Q-channel DAC is used in this IC in FM mode, all other CDMA circuits are disabled. The DAC output is filtered by a low-pass anti-aliasing filter. The filtered DAC output is the analog FM modulation signal, FM MOD. This signal modulates the frequency of this IC transmit VCO using external components when in FM RXTX Mode. 10.Operating Modes This IC has several modes of operation. The CDMA RXTX or FM RXTX modes are in effect when the telephone is making a call. IDLE mode is in effect when no call is in progress but the telephone receiver is active (ready to answer a call). SLEEP mode is a low-power mode in which the telephone cannot receive a call. This IC operating modes are defined by the states of three digital inputs: FMB, IDLEB, and SLEEPB. The power consumed by this IC is minimized by controlling these logic signals and disabling unused circuits. The selected circuits in this IC become active after the states of the operating mode controls are changed. 11.House Keeping ADC The House Keeping ADC provides DC measurement capability to the telephone. It is a low speed, 8-bit resolution, successive approximation analog-to-digital converter. It is designed to digitize DC voltages applied to the ADCIN pin from battery level, temperature, and other low frequency control or monitoring sensors. This ADC is in a power-down state during normal operation. It is activated by a positive-going pulse on ADCENBL. When this input is driven high, the House Keeping ADC powers up, samples and holds the voltage applied to ADCIN, and begins a conversion. The ADC output is available from a serial digital interface. Each of the eight data bits is valid (MSB first) during the rising edge of the ADCCLK output. A rising edge of ADCENBL during a conversion will be ignored. ADCENBL must be low and a conversion completed before a new conversion can be started. --25-- CXA3003R Notes of Operation 1. Signal operation The CXA3003R needs the master system clock "TCXO" that comes from a crystal oscillator at 19.68 MHz. A divide-by-4 derivative of TCXO called TCXO/4 operates as long as TCXO is active and power is applied to CXA3003R. Transmit and receive IF frequencies are generated by varactor-tuned TX and RX local oscillators on CXA3003R. CHIPx8, a derivative of TCXO is active for all operating modes except CDMA SLEEP and FM IDLE. 2. Receive IF Inputs The receive IF inputs, RXIF and RXIFB, differentially drive a input stage within the CXA3003R. The differential input impedance is nominally 500 . The IF signals receive by AC coupling. AC coupling capacitor values (0.001 F) are chosen to maximize the power transfer from receive IF circuitry. CXA3003R 6 From Receive RF Circuits 7 Fig. 9 Receive IF Inputs 3. Transmit IF Outputs The transmit IF outputs, TXIF and TXIFB, are differential outputs. The output impedance is low, 40 , nominally. These signals transfer to the subsequent transmit IF circuitry by using AC coupling. AC coupling capacitor values (0.001 F) are chosen to maximize the power transfer from the CXA3003R to the subsequent transmit IF circuitry. CXA3003R 11 To Transmit RF Circuits 12 Fig. 10 Transmit IF Outputs --26-- CXA3003R 4. VCOs In general terms, the frequency of oscillation, fo, for the VCOs is determined by: 1 2 LC fo = Where L and C are the net inductance and Capacitance of the external resonant tank circuit. The resonant tank circuit comprises inductor L connected in parallel with capacitance C. The tank circuit is connected between RXVCO T1 and RXVCO T2 (shown in Fig.11). Another tank circuit is connected between TXVCO T1 and TXVCO T2 (shown in Fig.12). The net capacitance of the tank circuit comprises a varactor diode (CV), an optional scaling capacitor connected (CV2) in parallel with the varactors, two DC blocking capacitors (CB) isolating the DC bias of the varactors from the CXA3003R, and pin-to-pin and pin-to-ground parasitic capacitors (CPP, CPG) (shown in Fig.13). The net tank capacitance is found from (CV2 + 1/2 * CV) x CB CPG + (CPP + ) (CV2 + 1/2 * CV) x 2 + CB 2 C= 15 External PLL Circuit 16 80 17 FM TX LPF VSC 2 OSC 18 40k 19 CXA3003R CXA3003R 3 Fig. 11 Receive VCO CPG CB Fig. 12 Transmit VCO CV CV2 CV L CPP CXA3003R CB CPG Fig. 13 VCO capacitors 5. Transmit VCO Synthesizer The transmit synthesizer consists of a VCO, a divide-by-two phase splitter, divide by R and N counters, and a phase detector. The VCO and divide-by-two generate the I and Q IF signals used to up-convert analog baseband to IF. The loop filter and tuning components are external to the CXA3003R. --27-- CXA3003R LO VCO Divider 1/2 to TX Modulator PD OUT Phase Detector Divider 1/106 Reference Divider n=16 19.68MHz from TCXO Fig. 14 Transmit VCO synthesizer 6. Transmit VCO Phase Detector The phase detector output, PD OUT, is the output of a dual mode bi-directional charge pump. It provides two levels of output current for frequency acquisition (175 A) and phase lock maintenance (16 A) after the VCO frequency is at or near its final frequency. The phase detector also provides a lock detect output, LOCK. This signal is low when unlocked, and high (high-impedance) when unused or in IDLE or SLEEP Modes. LOCK will indicate the unlocked condition until the VCO frequency is at its final value. LOCK will then toggle until phase lock has been established. The current available from PD OUT is set by an external resistor connected between PD ISET and ground (shown in Fig. 12). The value of the PD ISET resistor is determined by RPD = 0.64/IO Where Io is the current available for maintaining the transmit VCO frequency. During acquisition of the IF frequency, the current limit from PD OUT increases to 11 times that set by the resistor on PD ISET. A recommended Io of 16.3 A results in RPD=39 k 1 %. 7. FM Modulation Scaling The FMMOD output is used to frequency modulate the transmit VCO. The output voltage swing on FM MOD is normally 550 mVp-p. This modulating voltage must be scaled to achieve the required frequency deviation of the transmit VCO frequency when the CXA3003R is operating in FM mode. A 30 kHz deviation of the transmit VCO frequency translates into a 15 kHz deviation of the transmit IF frequency. A simple resistive voltage divider may be used as long as the total load on FM MOD is greater than 10 k. The output of the voltage divider drives the anode side of the varactor diodes (shown in Fig. 12). --28-- CXA3003R 8. TCXO The temperature-compensated crystal oscillator (TCXO) used in the telephone must provide a stable and accurate 19.68 MHz signal to the TCXO input of the CXA3003R. The specifications for this oscillator are outlined in table 1. Power Supply Voltage Output level Output load fout nominal frequency fout vs. temperature fout vs. power supply 3.3 V fout vs. load 0.8 Vp-p min fout phase noise 10 k min 10 pF max Frequency control range 19.68 MHz Control voltage range 2 ppm/C Control voltage input 0.3 ppm/V impedance Table 1 TCXO Oscillator requirements 0.2 ppm -120 dBc/Hz min (100 Hz offset) 23560 Hz +0.5 tp +2.5 V 100 k min 9. ADC and DAC Ranges All ADCs and DACs on the CXA3003R have internally-generated references which eliminate the need for additional adjustment or calibration of the ADCs and DACs. All ADCs and DACs employ offset-binary coding (Tables 2 and 3). The application of the House Keeping ADC is left up to the user. However, it can be useful for monitoring parameters such as battery voltage and temperature. The midpoint of the input voltage range of the House Keeping ADC is set to 1.5 V by an internal voltage reference. The input voltage range of the ADC is 2.0 V. The gain of the ADC approximately 7.8 V/step. Table 2 ADC Output Coding Input Voltage FM Receive ADC House Keeping ADC Greater than positive >2.500 full-scale Positive full-scale 2.500 99.6 % of full-scale 2.492 ...... ...... 50.2 % of full-scale 1.504 49.8 % of full-scale 1.496 ...... ...... 0.4 % of full-scale 0.508 Negative full-scale 0.500 Less than negative <0.500 full-scale Output Data MSB......LSB 1111 1111 1111 1111 1111 1110 ...... 1000 0000 0111 1111 ...... 0000 0001 0000 0000 0000 0000 Input Voltage CDMA Receive ADC Greater than positive full-scale Positive full-scale 93.7 % of full-scale ...... 53.3 % of full-scale 46.7 % of full-scale ...... 6.7 % of full-scale Negative full-scale Less than negative full-scale Output Data MSB...LSB 1111 1111 1110 ... 1000 0111 ... 0001 0000 0000 --29-- CXA3003R Table 3 DAC Input Coding Input Data MSB... ...LSB 1111 1111 1111 1110 ...... 1000 0000 0111 1111 ...... 0000 0001 0000 0000 Output Voltage FM Transmit DAC Positive full-scale 99.6 % of full-scale ...... 50.2 % of full-scale 49.8 % of full-scale ...... 0.4 % of full-scale Negative full-scale 10. ADC Offset Control The external DC voltages connected to IOFFSET and QOFFSET pins control the output of the CDMA and FM low-pass filters to the center of the CDMA and FM ADC input range, reducing the offset to zero. 11. Receive Low Pass Filters In CXA3003R, the receive low-pass filters remove residual IF frequency components and present baseband I and Q components to the ADCs. The CDMA baseband signal extends from 1 kHz to 630 kHz. The FM baseband signal extends from 100 Hz to 14 kHz. The low-pass filters reject frequency components above the passband while exhibiting a specific rate of attenuation in the transition band. For FM Receive Filters two external bypass capacitors are required between pin 31 and GND,and between pin 32 and GND as is shown in Fig.15. 31 0.01 0.01 32 Fig. 15 FM Receive Filter 12. Transmit Signal Path Low-Pass Filters Low-pass filters in the transmit signal path located after the transmit DACs attenuate much of the out-ofband frequency components created by digital-to-analog conversion process. These filters are relatively simple compared to the CDMA and FM low-pass filters found in the receive signal path. Since the gain of the transmit signal path is low, the offset at the filter outputs are less critical. Transmit filter offsets are not controlled as offsets are in the CDMA and FM receive paths. --30-- CXA3003R 13. Power Supply Considerations, Grounding, and Decoupling The CXA3003R is targeted for use in battery operated CDMA/FM portable cellular telephones. As such, the device has been designed to operate from a regulated 3.3 V power supply. The use of multiple voltage regulators is recommended throughout the telephone, but the CXA3003R should be powered from only one dedicated voltage regulator. Individual voltage regulators are usually assigned to the major circuit subsections within the (i.e. receive RF, transmit RF, power amplifier, CXA3003R, etc.) to reduce the possibility of signals from one subsection interfering with or distorting signals from another subsection. The voltage regulator used in telephone for the CXA3003R should be a linear voltage regulator, not a switching regulator. This is to keep power supply noise on the CXA3003R power inputs as low as possible. The recommended power supply voltage range of the CXA3003R is from 3.13 to 3.47 V (3.35 %). It is recommended that a 2 % accurate regulator be used so that the proper output voltage can be maintained over the temperature range of the telephone and over the power supply current range of the CXA3003R. Power supply decoupling around the CXA3003R is done with 0.01 F ceramic chip capacitors on each VDD pin. The capacitors are located as close to the pins as possible to minimize series inductance in the connection to the pin. The use of additional 0.001 F decoupling capacitors in parallel with the 0.01 F capacitors is recommended to further reduce high frequency noise on the power supply inputs to the CXA3003R. Although the CXA3003R has both analog and digital circuits and separate digital power and ground pins a single ground plane is recommended. The ground plane must overlap the footprint of the CXA3003R as much as possible. ALL CXA3003R ground pins must be connected to the same analog ground plane. --31-- Package Outline Unit : mm 80PIN LQFP (PLASTIC) 14.0 0.2 60 61 12.0 0.1 41 40 A 80 1 0.5 0.08 + 0.08 0.18 - 0.03 20 21 (0.22) + 0.2 1.5 - 0.1 + 0.05 0.127 - 0.02 0.1 0.1 0.1 0 to 10 0.5 0.2 NOTE: Dimension "" does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-80P-L01 QFP080-P-1212-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.5g --32-- 0.5 0.2 (13.0) |
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